Recently, in semiconductor devices, for optical communication or optical interconnection in which semiconductor chips are interconnected by an optical signal route, optical modules which each perform mutual transformation between an optical signal and an electric signal have been used frequently. In the latest optical modules, planar optical elements are used as components in many cases, and their optical coupling systems need positioning accuracy of equal to or less than several tens of micrometers. What has been developed as a semiconductor device using such an optical module is a device that has an optical signal input-output unit having such structure in which, when an optical module is mounted in a predetermined position of an optical printed circuit board or is mounted in a predetermined position of a photoelectric composite substrate which is equipped with an optical waveguide as an optical transmission medium, optical coupling between a planar optical element of the optical module and the optical waveguide is made. In regard to such an optical signal input-output mechanism, practical application is expected particularly in the optical interconnection field.
As one of conventional examples, there is a semiconductor device disclosed in Japanese Patent Laid-Open No. 2000-332301. FIG. 1 is a schematic partially sectional view of the semiconductor device of this conventional example. This semiconductor device has the structure of a chip-size package in which LSI chip 57, which makes up a semiconductor integrated circuit, and planar optical element array 61a in which planar optical elements are arranged two-dimensionally, are packaged in outside dimensions comparable to LSI chip 57. Printed wiring board 51 and mold resin 68 are used for the packaging. Printed wiring board 51 is equipped with optical waveguide 65 in addition to electric wiring 58. As for optical waveguide 65, each optical input-output section is arranged on a top face of optical waveguide 65 which faces planar optical element array 61a. For that purpose, a reflecting surface which is formed in one end of optical waveguide 65 so as to form an angle of 45° to input/output light of planar optical element array 61a is used. LSI chip 57 is implemented in a predetermined position on printed wiring board 51, and planar optical element array 61a is implemented in a predetermined position on LSI chip 57, through solder bumps 66, respectively. Thereby, each optical input-output surface section of planar optical element array 61a is optically coupled with each optical input-output section of optical waveguide 65 with their optical axes being mutually aligned. Micro-lens 62 is provided at each input-output surface section of planar optical element array 61a, and at each optical input-output section of optical waveguide 65.
As another example, there is a semiconductor device disclosed in Japanese Patent Laid-Open No.2001-185752. FIG. 2 is a schematic partially sectional view of the semiconductor device in this conventional example. In this semiconductor device, TBGA (Tape Ball Grid Arrays) package structure 79 which embeds LSI chip 77 and planar optical element array 81a is implemented on printed wiring board 71 through electric wiring layer 78 and solder balls 86. Each input-output surface section of planar optical element array 81ais optically coupled with an optical input-output section of optical waveguide 85 with their optical axes being mutually aligned by TBGA package structure 79 which is implemented in a predetermined position on printed wiring board 71 in which optical waveguide 85 is formed. Micro-lens 82 is provided at each input-output surface section of planar optical element array 81a, and at each optical input-output section of optical wave guide 65.
Nevertheless, in the structure illustrated in the above-described conventional examples, it is difficult to keep planar optical element arrays 61a and 81a and optical waveguides 65 and 85 in a state in which their optical axes are aligned against a temperature change because of the difference between the coefficients of thermal expansion of printed wiring boards 51 and 71 and LSI chips 57 and 77 on which planar optical element arrays 61a and 81a are mounted, or the like. In addition, when a plurality of planar optical element arrays 61a and 81a are provided, it is difficult to simultaneously perform optical axis adjustment of them, and in order to achieve it, an extremely highly precise mounting technique will be required, and it will lead to a cost increase.